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First 8-bit microprocessor. Implemented an instruction set with programmable computer terminals that utilised additional Intergrated Circuits to produce a computer-based control system.
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Timeline emphazizing the brands of common consumer targeted processors implementing the x86 instruction set.
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First x86 microprocessors that consisted of a 16-bit microprocessor chips. 8088 and the subsequent clones were a variant of the 8086 with an 8-bit data path and 8-bit support and peripheral chips. The 8086 gave rise to the x86 architecture which eventually turned out as Intel's most successful line of processors.
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Also known as i386 or just 386. First 32-bit microprocessor with a Memorty Management Unit or MMU and a paging translation unit, which made it easier to implement operating systems that used virtual memory. Also supported hardware debugging.
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First Intel Pentium microprocessor that was Intel's fifth generation and first superscalar arichitecture that incorporated instruction level parallelism within a single processor. Also included a wider data bus (64-bit) with a CPU cache that minimized the average time to access memory in order to reduce the latency for address calculation.
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Successor of the original Pentium edition. Introduced the 6th generation Intel x86 microarchitecture. Featured out of order execution, including speculative execution via register renaming. Had a wide 36-bit address bus allowing it to access up to 64GB of memory.
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Seventh generation x86 processor. First of its kind. Dynamically runs micro-instructions at runtime. Out of order execution CPU design with double data rate (DDR) technology.
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First Intel Processor to use a 32-bit dual-core mobile (low power) microprocesssor with 36-bit Physical Address Extension. An enhanced version of the Intel Pentium microarchitecture.
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First of Intel's 64-bit version of the x86 instruction set with single, dual, and quad-core microprocessors based on the Intel Core microarchitecture with a 40-bit Phyiscal Address Extension capability. Features include low power consumption and lower clock-cycle frequency.
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Based on the Nehalem microprocessor architecture that uses an integrated DDR3 memory controller, a QuickPath Interconnect (QPI) processor interconnect with new I/O chipsets and mainboards.
